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| White Electronic Designs 128KX32 SRAM/FLASH MODULE FEATURES Access Times of 25ns (SRAM) and 70, 90 and 120ns (FLASH) Packaging: 66-pin, PGA Type, 1.385 inch square HIP, Hermetic Ceramic HIP (Package 402) 128Kx32 SRAM 128Kx32 5V Flash Organized as 128Kx32 of SRAM and 128Kx32 of Flash Memory with common Data Bus Low Power CMOS Commercial, Industrial and Military Temperature Ranges TTL Compatible Inputs and Outputs Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Weight - 13 grams typical PRELIMINARY* WSF128K32-XH2X FLASH MEMORY FEATURES 10,000 Erase/Program Cycles Sector Architecture 8 equal size sectors of 16K bytes each Any combination of sectors can be concurrently erased. Also supports full chip erase 5 Volt Programming; 5V 10% Supply Embedded Erase and Program Algorithms Hardware Write Protection Page Program Operation and Internal Program Control Time. * This data sheet describes a product under development, not fully characterized, and is subject to change without notice. Note: Programming information available upon request. FIG. 1 1 I/O8 I/O9 I/O10 A14 A16 A11 A0 NC I/O0 I/O1 I/O2 11 22 12 PIN CONFIGURATION FOR WSF128K32-XH2X TOP VIEW 23 FWE2 SWE2 GND I/O11 A10 A9 A15 VCC FCS SCS I/O3 33 I/O15 I/O14 I/O13 I/O12 OE NC FWE1 I/O7 I/O6 I/O5 I/O4 I/O24 I/O25 I/O26 A7 A12 SWE1 A13 A8 I/O16 I/O17 I/O18 44 34 VCC SWE4 FWE4 I/O27 A4 A5 A6 FWE3 SWE3 GND I/O19 55 45 I/O31 I/O30 I/O29 I/O28 A1 A2 A3 I/O23 I/O22 I/O21 I/O20 66 OE A0-16 SCS FCS FWE1 SWE1 56 PIN DESCRIPTION D0-31 A0-16 SWE1-4 SCS OE VCC GND NC FWE1-4 FCS Data Inputs/Outputs Address Inputs SRAM Write Enables SRAM Chip Select Output Enable Power Supply Ground Not Connected Flash Write Enables Flash Chip Select BLOCK DIAGRAM FWE2 SWE2 FWE3 SWE3 FWE4 SWE4 128K x 8 Flash 128K x 8 SRAM 128K x 8 Flash 128K x 8 SRAM 128K x 8 Flash 128K x 8 SRAM 128K x 8 Flash 128K x 8 SRAM I/O0-7 I/O8-15 I/O16-23 I/O24-31 October 2002 Rev. 4 1 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature Storage Temperature Signal Voltage Relative to GND Junction Temperature Supply Voltage Parameter Flash Data Retention Flash Endurance (write/erase cycles) 10 years 10,000 Test OE Capacitance F/S WE 1-4 Capacitance F/S CS Capacitance D0-31 Capacitance Unit V V V A0 - A16 Capacitance Symbol TA TSTG VG TJ VCC -0.5 Min -55 -65 -0.5 Max +125 +150 7.0 150 7.0 Unit C C V C V SCS H L L L OE X L H X SWE X H H L WSF128K32-XH2X SRAM TRUTH TABLE Mode Standby Read Read Write Data I/O High Z Data Out High Z Data In Power Standby Active Active Active NOTE: 1. FCS must remain high when SCS is low. CAPACITANCE (TA = +25C) Symbol COE CWE CCS CI/O CAD Condition Max Unit pF pF pF pF pF VIN = 0V, f = 1.0MHz 80 VIN = 0V, f = 1.0MHz 30 VIN = 0V, f = 1.0MHz 50 VIN = 0V, f = 1.0MHz 30 VIN = 0V, f = 1.0MHz 80 NOTE: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.5 2.2 -0.5 Max 5.5 VCC + 0.3 +0.8 This parameter is guaranteed by design but not tested. DC CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55C TO +125C) Parameter Input Leakage Current Output Leakage Current SRAM Operating Supply Current x 32 Mode Standby Current SRAM Output Low Voltage SRAM Output High Voltage Flash VCC Active Current for Read (1) Flash VCC Active Current for Program or Erase (2) Flash Output Low Voltage Flash Output High Voltage Flash Output High Voltage Flash Low VCC Lock Out Voltage Symbol ILI ILO ICCx32 ISB VOL VOH ICC1 ICC2 VOL VOH1 VOH2 VLKO Conditions VCC = 5.5, VIN = GND to VCC SCS = VIH, OE = VIH, VOUT = GND to VCC SCS = VIL, OE = FCS = VIH, f = 5MHz, VCC = 5.5 FCS = SCS = VIH, OE = VIH, f = 5MHz, VCC = 5.5 IOL = 8mA, VCC = 4.5 IOH = -4.0mA, VCC = 4.5 FCS = VIL, OE = SCS = VIH FCS = VIL, OE = SCS = VIH IOL = 8.0mA, VCC = 4.5 IOH = -2.5 mA, VCC = 4.5 IOH = -100 A, VCC = 4.5 0.85 x VCC VCC -0.4 3.2 2.4 220 280 0.45 Min Max 10 10 670 80 0.4 Unit A A mA mA V V mA mA V V V V NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V White Electronic Designs Corporation Phoenix AZ (602) 437-1520 2 White Electronic Designs SRAM AC CHARACTERISTICS (VCC = 5.0V, TA = -55C TO +125C) Parameter Read Cycle Read Cycle Time Address Access Time Output Hold from Address Change Chip Select Access Time Output Enable to Output Valid Chip Select to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z tRC tAA tOH tACS tOE tCLZ 1 tOLZ 1 tCHZ 1 tOHZ 1 3 0 12 12 0 25 15 Symbol Min 25 25 -25 Max ns ns ns ns ns ns ns ns ns Unit WSF128K32-XH2X SRAM AC CHARACTERISTICS (VCC = 5.0V, TA = -55C TO +125C) Parameter Write Cycle Write Cycle Time Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse Width Address Setup Time Address Hold Time Output Active from End of Write Write Enable to Output in High Z Data Hold from Write Time tWC tCW tAW tDW tWP tAS tAH tOW 1 tWHZ 1 tDH 0 Symbol Min 25 20 20 15 20 0 0 3 15 -25 Max ns ns ns ns ns ns ns ns ns ns Unit 1. This parameter is guaranteed by design but not tested. 1. This parameter is guaranteed by design but not tested. FIG. 2 AC TEST CIRCUIT Parameter I OL Current Source AC TEST CONDITIONS Typ VIL = 0, VIH = 3.0 5 1.5 1.5 Unit V ns V V Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level D.U.T. C eff = 50 pf VZ 1.5V (Bipolar Supply) I OH Current Source Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 W. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. 3 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com White Electronic Designs FIG. 3 SRAM TIMING WAVEFORM - READ CYCLE WSF128K32-XH2X tRC ADDRESS tAA SCS tRC ADDRESS tACS tCLZ SOE tCHZ tAA tOH DATA I/O PREVIOUS DATA VALID DATA VALID tOE tOLZ DATA I/O HIGH IMPEDANCE tOHZ DATA VALID READ CYCLE 1, (SCS = OE = VIL, SWE = FCS = VIH) READ CYCLE 2, (SWE = FCS = VIH) FIG. 4 SRAM WRITE CYCLE - SWE CONTROLLED tWC ADDRESS tAW tCW SCS tAH tAS SWE tWP tOW tWHZ tDW tDH DATA I/O DATA VALID WRITE CYCLE 1, SWE CONTROLLED (FCS = VIH) FIG. 5 SRAM WRITE CYCLE - SCS CONTROLLED tWC ADDRESS WS32K32-XHX tCW tAH tAS SCS tAW tWP SWE tDW DATA I/O DATA VALID tDH WRITE CYCLE 2, SCS CONTROLLED (FCS = VIH) White Electronic Designs Corporation Phoenix AZ (602) 437-1520 4 White Electronic Designs WSF128K32-XH2X FLASH AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS, FWE CONTROLLED (VCC = 5.0V, TA = -55C TO +125C) Parameter Write Cycle Time Chip Select Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Select Hold Time Write Enable Pulse Width High Duration of Byte Programming Operation (min) Chip and Sector Erase Time Read Recovery Time Before Write VCC Set-up Time Chip Programming Time Output Enable Setup Time Output Enable Hold Time (1) 1. For Toggle and Data Polling. tOES tOEH 0 10 Symbol Min tAVAV tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHEH tWHWL tWHWH1 tWHWH2 tGHWL tVCS tWC tCS tWP tAS tDS tDH tAH tCH tWPH 70 0 35 0 30 0 45 0 20 14 2.2 0 50 12.5 0 10 60 -70 Max Min 90 0 45 0 45 0 45 0 20 14 2.2 0 50 12.5 0 10 60 -90 Max Min 120 0 50 0 50 0 50 0 20 14 2.2 0 50 12.5 60 -120 Max ns ns ns ns ns ns ns ns ns s sec s s sec ns ns Unit FLASH AC CHARACTERISTICS READ ONLY OPERATIONS (VCC = 5.0V, TA = -55C TO +125C) Parameter Read Cycle Time Address Access Time Chip Select Access Time OE to Output Valid Chip Select to Output High Z (1) OE High to Output High Z (1) Output Hold from Address, FCS or OE Change, whichever is first 1. Guaranteed by design, not tested. Symbol Min tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tDF tDF tOH 0 70 70 70 35 20 20 0 -70 Max Min 90 90 90 40 25 25 0 -90 Max Min 120 120 120 50 30 30 ns -120 Max ns ns ns ns ns ns Unit 5 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com White Electronic Designs WSF128K32-XH2X FLASH AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS, FCS CONTROLLED (VCC = 5.0V, TA = -55C TO +125C) Parameter Write Cycle Time FWE Setup Time FCS Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time FWE Hold from FWE High FCS Pulse Width High Duration of Programming Operation Duration of Erase Operation Read Recovery before Write Chip Programming Time Symbol tAVAV tWLEL tELEH tAVEL tDVEH tEHDX tELAX tEHWH tEHEL tWHWH1 tWHWH2 tGHEL tWC tWS tCP tAS tDS tDH tAH tWH tCPH Min 70 0 35 0 30 0 45 0 20 14 2.2 0 12.5 60 -70 Max Min 90 0 45 0 45 0 45 0 20 14 2.2 0 12.5 60 -90 Max Min 120 0 50 0 50 0 50 0 20 14 2.2 0 12.5 60 -120 Max Unit ns ns ns ns ns ns ns ns ns s sec ns sec White Electronic Designs Corporation Phoenix AZ (602) 437-1520 6 White Electronic Designs WSF128K32-XH2X FIG. 6 AC WAVEFORMS FOR FLASH MEMORY READ OPERATIONS tDF tOH Addresses Stable tRC tOE tACC tCE OE FWE Addresses NOTE: SCS = VIH 7 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com Outputs FCS High Z Output Valid High Z White Electronic Designs WSF128K32-XH2X FIG. 7 WRITE/ERASE/PROGRAM OPERATION, FLASH MEMORY FWE CONTROLLED tOH tDF tRC tOE PA Data Polling tAH tWHWH1 PA tAS tWPH tDH 5555H tGHWL tWC tWP tCS A0H PD D7 DOUT NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 6. SCS = VIH Addresses FWE FCS OE tDS White Electronic Designs Corporation Phoenix AZ (602) 437-1520 8 5.0 V Data tCE White Electronic Designs WSF128K32-XH2X FIG. 8 AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR FLASH MEMORY SA 2AAAH 5555H 2AAAH 5555H tWPH 5555H tWP AAH tDS tAS tGHWL tCS tDH 55H tAH 80H AAH 55H 10H/30H OE Addresses FWE FCS Notes: 1. SA is the sector address for Sector Erase. 2. SCS = VIH Data 9 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com VCC tVCS White Electronic Designs WSF128K32-XH2X FIG. 9 AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS FOR FLASH MEMORY High Z tDF D7 = Valid Data D0-D7 Valid Data tOH D0-D6 = Invalid tOE tWHWH 1 or 2 D7 D7 D7 tWHWH 1 or 2 tOE tCH tOEH tCE FWE FCS OE Note: SCS = VIH White Electronic Designs Corporation Phoenix AZ (602) 437-1520 10 D0-D6 D7 D7 Valid Data High Z White Electronic Designs WSF128K32-XH2X FIG. 10 WRITE/ERASE/PROGRAM OPERATION FOR FLASH MEMORY, CS CONTROLLED PA Data Polling tAH tWHWH1 PA tAS tGHEL tCP tCPH tDH A0H 5555H tWC tWS PD FWE OE FCS Data tDS Addresses D7 DOUT NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence. 6. SCS = VIH 11 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com 5.0 V White Electronic Designs 35.2 (1.385) 0.38 (0.015) SQ WSF128K32-XH2X PACKAGE 402: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2) PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM 25.4 (1.0) TYP 5.7 (0.223) MAX 3.81 (0.150) 0.1 (0.005) 2.54 (0.100) TYP 1.27 (0.050) 0.1 (0.005) 0.76 (0.030) 0.1 (0.005) 15.24 (0.600) TYP 1.27 (0.050) TYP DIA 0.46 (0.018) 0.05 (0.002) DIA 25.4 (1.0) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION W S F 128K32 - XX H2 X X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: M = Military Screened I = Industrial C = Commercial -55C to +125C -40C to +85C 0C to +70C PACKAGE TYPE: H2 = Ceramic Hex In-line Package, HIP (Package 402) ACCESS TIME (ns) 22 = 25ns SRAM and 120ns FLASH 29 = 25ns SRAM and 90ns FLASH 27 = 25ns SRAM and 70ns FLASH ORGANIZATION, 128K x 32 Flash PROM SRAM WHITE ELECTRONIC DESIGNS CORP. White Electronic Designs Corporation Phoenix AZ (602) 437-1520 12 |
Price & Availability of WSF128K32-27H2CA
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